1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory having a number of memory cells each connected to a selected word line and a selected pair of digit lines and a current-voltage converting circuit connected through a pair of read bus lines to the digit line pairs.
2. Description of related art
In conventional semiconductor memories, each memory cell is connected to a pair of digit lines respectively pulled up by a pair of load transistors. The pair of digit lines are respectively connected to a sense amplifier and are also connected to a pair of driving transistors, respectively. The pair of digit lines are also connected to a pair of read bus lines, which are also connected with a number of pairs of similar digit lines. The pair of read bus lines are also connected to a current-voltage converter.
When a memory cell is selected, data read out of the selected memory cell is transferred by means of the associated sense amplifier to the pair of read bus lines in the form of a potential difference between the pair of read bus lines, which is converted into a voltage signal by the current-voltage converter.
In the above mentioned semiconductor memory, the larger the memory size or capacitor becomes, the longer the read bus lines become, and therefore, wiring resistance of the read bus lines becomes significant. This means that a potential difference between the pair of read bus lines at a position most remote from the current-voltage converter becomes noticeably larger than a potential difference between the pair of read bus lines at a location of the read bus lines closest to the current-voltage converter.
On the other hand, each of the read bus lines is connected with collectors of a number of bipolar transistors respectively included in a number of sense amplifiers connected to the pair of read bus lines. A total of collector capacitances of these transistors become a substantial amount. As a result, the read bus lines have a substantial capacitance. This capacitance is charged and discharged by a voltage amplitude occurring between the pair of read bus lines. Because of this charging and discharging, some delay occurs after an inversion of the voltage difference between the pair of digit lines until an inversion of the voltage difference between a pair of output lines of the current-voltage converter.
This delay gives a delay to a reading speed or time in this type of semiconductor memory. When the memory size or capacity is increased, the number of the sense amplifiers connected to the read bus lines correspondingly increases, and therefore, the capacitance of the read bus lines also increases. As a result, the above mentioned delay becomes more remarkable, and therefore, the reading speed of the memory decreases remarkably.